The present invention relates to field oxide isolated, extrinsic base bipolar devices and in particular to a method utilizing a single polycrystalline silicon layer whereby respective vertical emitter/base junctions and horizontal extrinsic base/emitter spacings may be scaled relative to one another.
With the ever present demands of the computer industry for performance improvements and enhanced functionality has come a desire to improve upon device construction and integrated circuit processing techniques so as to achieve methodologies and devices that lend themselves to high packing densities, optimal performance parameters and high processing yields. In the field of bipolar devices and, in particular, field oxide isolated devices, device performance can be improved by more critically controlling the vertical structure of the emitter/base junction as well as the horizontal spacing between the extrinsic base and emitter regions.
In this regard, polycrystalline silicon (hereinafter also referred to as poly silicon) has found a number of uses in various processes for achieving self-aligned devices and one of which is disclosed in U.S. Pat. No. 4,437,897. There a combined layer of polycrystalline silicon and silicon dioxide are used in a single base implant process for controlling the geometry of the extrinsic base regions. The polysilicon is also used in combination with subsequent nitride and oxide layers, an emitter etch and an emitter implant to achieve a shallow emitter/base junction and wherein a portion of the junction is also contained within the poly silicon.
Still other bipolar processes using polycrystalline silicon in the control of base/emitter geometries are disclosed in a paper by Sakai et. al., Elevated Electrode Integrated Circuits, IEEE Transactions of Electron Devices, Vol. Ed-24, No. 4, April, 1979, pp. 379-384; a book, edited by L. Esaki and G. Soncini, Large Scale Integrated Circuits Technology: State of the Art and Prospects (Martinus, Nijhoff, The Hague, 1982), pp. 381-384; a paper by Vora et. al., A 2 Micron High Performance Bipolar 64K ECL Static RAM Technology with 200 Square Microns Contactless Memory Cell, IEDM (1984), pp. 690-693; and a paper by Ashburn et. al., Comparison of Experimental and Theoretical Results on the Poly Silicon Emitter Bipolar Transmitters, 31 IEEE Transactions on Electron Devices, pp. 853-859 (July, 1984).
In each of the latter publications, poly silicon is used as a diffusion source during device processing, although in a different fashion from the present invention, to achieve self-aligned base emitter regions with shallow emitter junctions. It is also to be noted that the latter Ashburn paper discloses the growth of a chemical oxide intermediate the epitaxial layer and the poly silicon in the region of the emitter and whereby improved transmistor gains are obtained.
One other feature of note which is commonly used in the construction of field oxide isolated bipolar transistors is a so-called channel stopper and which is typically implanted beneath the field oxide to reduce parasitic collector-substrate capacitance. Specifically and as noted in U.S. Pat. No. 4,437,897, a channel stopper is provided about each active site in horizontal coextensive relation to the field oxide. While the channel stoppers are also commonly coupled to one another in the form of a matrix, it has been discovered that by separating each channel stopper from the sub-collector of each active site that parasitic device capacitance can be reduced. Until the present invention though, a barrier or limit has existed to the possible reduction of this capacitance, due to the attendant out-diffusion or auto doping that is believed to occur during the annealing of the implanted channel stopper.